Table of Contents
1 Cover
5 Preface
7 1 Coding and Addressing Modes 1.1. Encoding and formatting an instruction 1.2. Addressing modes 1.3. Conclusion
8 2 Instruction Set and Class 2.1. Definitions 2.2. Transfer instructions 2.3. Data processing instructions 2.4. Control transfer instructions 2.5. Environmental instructions 2.6. Parallelism instructions 2.7. Extensions to instruction sets 2.8. Various instructions 2.9. Conclusion
9 3 Additional Concepts 3.1. Concepts associated with the instruction set and programming 3.2. Concepts linked to execution 3.3. Hardware and software compatibilities 3.4. Measuring processor performances 3.5. Criteria for choosing 3.6. Conclusion
10 4 Subroutine 4.1. Stack memory 4.2. Subroutine 4.3. Conclusion
11 5 Interrupt Mechanism 5.1. Origin, definition and classification 5.2. External causes 5.3. Nested interrupts 5.4. Internal causes 5.5. Debugging 5.6. Priority between internal and external interrupts 5.7. Identification of the source and vectorization 5.8. Nested and queued interrupts 5.9. Uses 5.10. Interrupts and execution modes 5.11. Interrupts and advanced architectures 5.12. Conclusion
13 Exercises
14 Appendix
15 Acronyms
16 References
17 Index
List of Illustrations
1 Chapter 1Figure 1.1. Breakdown of an instructionFigure 1.2. An example of the structure of an operation codeFigure 1.3. Format of an instruction with two operandsFigure 1.4. An instruction with several operandsFigure 1.5. Three fixed formats for MIPS instructionsFigure 1.6. Typical instruction format from 8086/88Figure 1.7. Variable instruction format Intel IA-32 and Intel 64 (Intel 2016) ar...Figure 1.8. Instruction with an operand fieldFigure 1.9. Execution of an instruction using register addressing from one regis...Figure 1.10. Instruction with direct addressingFigure 1.11. Instruction with an address at page 0Figure 1.12. Execution of an instruction in relative addressingFigure 1.13. Seeking an operand in relative addressingFigure 1.14. Instruction with indirect register addressingFigure 1.15. Instruction with indirect memory addressingFigure 1.16. Execution of an instruction in indexed addressing with displacement...Figure 1.17. Execution of an instruction in indexed addressing with displacement...Figure 1.18. Execution of an instruction in base addressing with displacementFigure 1.19. Indirect indexed addressing or pre-indexingFigure 1.20. Indirect indexed addressing or post-indexingFigure 1.21. Indirect indexed zero-page addressing of MCS6502Figure 1.22. Execution of an instruction in bit addressingFigure 1.23. Window of five samplesFigure 1.24. Circular bufferFigure 1.25. Comparison between linear and circular addressings (from Rao (2001)...Figure 1.26. Flow diagram of the algorithm of an 8-point FFT DIT in base 2
2 Chapter 2Figure 2.1a. Instruction
