at higher switching frequency, the inverter will have smaller filter size and smaller loss on the filter in UPS and smaller DC‐side film capacitor in EV power train. In addition, we can get better dynamics. In some applications of ultra‐high‐speed drives for the industry or aeronautics, inverters are required to operate at very high switching frequency to provide lower ripple fundamental frequency current to the motor/generators. It seems higher switching frequency operating has advantage. What is the maximum switching frequency the inverter can operate at?
Actually, the switching frequency is limited by loss of the power semiconductor devices in the inverter. Figure 1.6 shows loss of the power semiconductor switches of the inverter of 100 kVA UPS exampled in the last section. Typical Insulated Gate Bipolar Transistor (IGBT) devices (Si IGBT FF300R12KT) are used as the switches. The loss of the inverter power semiconductor devices is composed of conduction loss, turn‐on loss, turn‐off loss, and reverse recovery loss. Conduction loss is static loss, which does not change with the switching frequency shown as the black part of the bar at the bottom of the figure. The other three losses – turn‐on loss, turn‐off loss, and reverse recovery loss – are dynamic losses, which increase linearly with the switching frequency as shown in the figure. As a result the dynamic loss of the power device depends on the switching frequency. If we want to design the inverter with required efficiency, its maximum switching frequency should be restricted to constrain total power device loss to certain value. Dynamic loss has another commonly used name: switching loss. It means the loss is caused by the device switching actions, either turning on or turning off.
For the same inverter parameters, when SiC MOSFET (CAS300M12BM2) is used, total SiC MOSFET loss of the inverter vs. the switching frequency is shown in Figure 1.7. Since the recovery loss is smaller, it is ignored. The loss of the inverter power semiconductor devices is composed of conduction loss, turn‐on loss, and turn‐off loss. Similar to the IGBT inverter, the conduction loss is constant while the dynamic loss is proportional to the switching frequency. Although the power device loss of the SiC inverter loss is much smaller than that of the IGBT inverter, the dynamic loss is still the main factor to limit the upper switching frequency.
Figure 1.6 Power semiconductor loss of the inverter vs. switching frequency.
Figure 1.7 Total SiC MOSFET loss of the inverter vs. switching frequency.
As a result, conducting loss is almost constant while switching loss increases with switching frequency. Actually, the voltage and the current of the power device have an overlap time during the switching transient process, which causes switching losses. The average switching loss is proportional to the switching frequency. To get an expected conversion efficiency, the switching frequency of inverters needs to be restricted. This type of converter is called hard‐switching converter. Hard‐switching converters can operate only at lower switching frequency. Lower switching frequency operation in turn results in bulkier passive components and higher audible noise. The wall to prevent the switching frequency from increasing is due to the switching loss. Can we reduce the switch loss of the inverter so that it can operate at higher switching frequency? To realize this goal, a technology to shape voltage and current of the power device during switching transient process, known as soft‐switching, occurs. Before a power device in a converter changes its status, either from on‐state to off‐state or from off‐sate to on‐state, the voltage across it or the current through it is set to zero with the help of the resonance between inductance and capacitance in the circuit. Soft‐switching is able to reduce the switching loss of the power semiconductor devices so that the converter can operate at higher switching frequency.
1.2 Concept of Soft‐switching Technique
A power device undergoes a switching transient process during its turn‐on as shown in Figure 1.8. From time t1 to t2, both voltage uS1 across the device S1 and current iS1 through it have high values during turn‐on transient process. The voltage and current overlap on the device occurs during switch turn‐on process, which results in turn‐on loss. The turn‐on loss Eon is equal to integral of multiplication of the voltage uS1 across the device S1 and the current iS1 through it in the turn‐on transient duration. Similarly, when the device turns off, it also undergoes a turn‐off transient process. The voltage and current overlap on the device occurs in the switch turn‐off process, which results in turn‐off loss Eoff.
To reduce the turn‐on and turn‐off loss of the power device, soft‐switching techniques occur. The soft‐switching technique is a way to shape voltage and current of the power device during switching transient process by changing converter topology and/or introducing a unique control. Thus the overlapping of voltage and current on the power device during switching commutations is reduced. It not only reduces switching loss but also suppresses voltage stress on the power devices and electromagnetic interference (EMI) noise.
Figure 1.8 Typical switching waveforms of a power device.
1.2.1 Soft‐switching Types
Soft‐switching techniques are realized with innovated converter topologies and/or by introducing a unique control. There are many soft‐switching converter topologies and their control methods. Soft‐switching techniques can be summarized as four types as follows.
Zero‐Voltage‐Switching Turn‐on (ZVS‐on): During a power semiconductor device turn‐on process, voltage applied on the power device decreases almost to zero before the gate drive signal jumps to the high level for turning on the device. Thus the voltage and current overlapping of the device during turn‐on transient process is eliminated. As shown in Figure 1.9, voltage uS1 on the device S1 is set to zero before its gate drive signal ug1 goes to the high level. Typically, a diode is antiparalleled with device S1. Once voltage uS1 on the device S1 decreases to zero, the antiparalleled diode D1 will conduct. It creates zero voltage turn‐on condition for the device S1. Thus the overlapping of voltage and current of the power device during turn‐on process is got rid of. The integral of multiplication of uS1 and iS1 during turn‐on process becomes zero. Thus turn‐on loss of the device is avoided. ZVS‐on is ideal turn‐on process since it has no turn‐on loss.
Zero‐Current‐Switching Turn‐on (ZCS‐on): During a power device turn‐on process, its current gradually increases from zero value while its voltage quickly goes down. Thus the voltage and current overlapping of the device during turn‐on transient process is reduced. As shown in Figure 1.10, when gate drive signal steps up, the current iS1 of the
