Digital VLSI Design and Simulation with Verilog. Suman Lata Tripathi

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       Dr. Suman Lata Tripathi

       Lovely Professional University, Phagwara, Punjab, India

       Dr. Sobhit Saxena

       Lovely Professional University, Phagwara, Punjab, India

       Dr. Sanjeet Kumar Sinha

       Lovely Professional University, Phagwara, Punjab, India

       Dr. Govind Singh Patel

       IIMT College of Engineering, Greater Noida, UP, India

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      The right of Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, and Govind Singh Patel to be identified as the authors of this work has been asserted in accordance with law.

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       Library of Congress Cataloging-in-Publication Data

      Names: Tripathi, Suman Lata, author. | Saxena, Sobhit, author. | Sinha, Sanjeet Kumar, author. | Patel, Govind Singh, author.

       Title: Digital VLSI design and simulation with Verilog / Suman Lata Tripathi, Sobhit Saxena, Sanjeet Kumar Sinha, Govind Singh Patel.

       Description: Hoboken, NJ : John Wiley & Sons, 2022. | Includes bibliographical references and index.

       Identifiers: LCCN 2021020790 (print) | LCCN 2021020791 (ebook) | ISBN 9781119778042 (hardback) | ISBN 9781119778066 (pdf) | ISBN 9781119778080 (epub) | ISBN 9781119778097 (ebook)

      Subjects: LCSH: Integrated circuits--Very large scale integration--Design and construction. | Verilog (Computer hardware description language)

      Classification: LCC TK7874.75 .T75 2022 (print) | LCC TK7874.75 (ebook) | DDC 621.39/5028553--dc23

      LC record available at https://lccn.loc.gov/2021020790 LC ebook record available at https://lccn.loc.gov/2021020791

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      Cover design by Wiley

      Set in 9.5/12.5 STIXTwoText by Integra Software Services Pvt. Ltd, Pondicherry, India

      1  Cover

      2  Title page

      3  Copyright

      4  Preface

      5  About the Authors

      6 1 Combinational Circuit Design1.1 Logic Gates1.1.1 Universal Gate Operation1.1.2 Combinational Logic Circuits1.2 Combinational Logic Circuits Using MSI1.2.1 Adders1.2.2 Multiplexers1.2.3 De-multiplexer1.2.4 Decoders1.2.5 Multiplier1.2.6 Comparators1.2.7 Code Converters1.2.8 Decimal to BCD EncoderReview QuestionsMultiple Choice QuestionsReference

      7 2 Sequential Circuit Design2.1 Flip-flops (F/F)2.1.1 S-R F/F2.1.2 D F/F2.1.3 J-K F/F2.1.4 T F/F2.1.5 F/F Excitation Table2.1.6 F/F Characteristic Table2.2 Registers2.2.1 Serial I/P and Serial O/P (SISO)2.2.2 Serial Input and Parallel Output (SIPO)2.2.3 Parallel Input and Parallel Output (PIPO)2.2.4 Parallel Input and Serial Output (PISO)2.3 Counters2.3.1 Synchronous Counter2.3.2 Asynchronous Counter2.3.3 Design of a 3-Bit Synchronous Up-counter2.3.4 Ring Counter2.3.5 Johnson Counter2.4 Finite State Machine (FSM)2.4.1 Mealy and Moore Machine2.4.2 Pattern or Sequence DetectorReview QuestionsMultiple Choice QuestionsReference

      8 3 Introduction to Verilog HDL3.1 Basics of Verilog HDL3.1.1 Introduction to VLSI3.1.2 Analog and

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