demultiplexer
Figure 5.8 shows the design of a quantum 1-to-8 demultiplexer. As a consequence of the design of the quantum demultiplexer, a 1-to-2n quantum demultiplexer can be constructed using a 1-to-2n−1 quantum demultiplexer and 2n−1 quantum Fredkin gates, which is shown in figure 5.9. The properties of the 1-to-2n quantum demultiplexer are given in property 5.2.
Figure 5.8. The quantum 1-to-8 demultiplexer.
Figure 5.9. Block diagram of a 1-to-2n demultiplexer.
Property 5.2. A quantum 1-to-2n demultiplexer can be designed with 2n−1 gates which produce n garbage outputs. It also requires a 5(2n−1) quantum cost and a delay of 5(2n−1)Δ, where n denotes the number of selection inputs and Δ denotes the unit delay.
5.3 Summary
In this chapter the quantum multiplexer (MUX) and demultiplexer (DEMUC) are presented and explained with the quantum circuit representation. In the multiplexer section, a 2-to-1 MUX, 4-to-1 MUX, and 8-to-1 MUX are described and generalized to the 2n-to-1 multiplexer. In the demultiplexer section, a 1-to-2 DEMUX, 1-to-4 DEMUX, and 1-to-8 DEMUX are described and generalized to the 1-to-2n demultiplexer. Moreover, the quantum cost and delay of the multiplexers and demultiplexers are provided.
Further reading
[1] Haghparast M and Monfared A T 2017 Novel quaternary quantum decoder, multiplexer and demultiplexer circuits Int. J. Theor. Phys. 56 1694–707
[2] Khan M H A 2008 Reversible realization of quaternary decoder, multiplexer, and demultiplexer circuits 38th Int. Symp. on Multiple Valued Logic pp 208–13
[3] Mardiris V A and Karafyllidis I G 2010 Design and simulation of modular 2n to 1 quantum-dot cellular automata (QCA) multiplexers Int. J. Circuit Theory Appl. 38 771–85
IOP Publishing
Quantum Computing
A pathway to quantum logic design
Hafiz Md Hasan Babu
Chapter 6
Quantum adder circuits
Several types of adders are used in computing systems, such as carry skip adders (CSAs), binary coded decimal (BCD) adders, and so on. Among them the most common is the ripple carry adder, in which full-adders are connected in series and carry is propagated through all the stages and hence requires more carry propagation time to generate the carry output. Carry look ahead adders are the fastest of all the adders since the carry output is generated in parallel computation, but this requires a large number of gates. The CSA is the most promising adder which presents a compromise between hardware and performance compared to both adders mentioned above. In the full-adder operation, if either of the inputs is a logical one, then the cell will propagate the carry input to the carry output. Hence the i
Конец ознакомительного фрагмента.
Текст предоставлен ООО «ЛитРес».
Прочитайте эту книгу целиком, купив полную легальную версию на ЛитРес.
Безопасно оплатить книгу можно банковской картой Visa, MasterCard, Maestro, со счета мобильного телефона, с платежного терминала, в салоне МТС или Связной, через PayPal, WebMoney, Яндекс.Деньги, QIWI Кошелек, бонусными картами или другим удобным Вам способом.
