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      1  Cover

      2  Title Page

      3  Copyright Page

      4  Preface

      5  Acknowledgements

      6  About the Companion Website

      7  Guide to Supplementary Resources

      8  1 Introduction to Finite State Machines 1.1 SOME NOTES ON STYLE

      9  2 Using FSMs to Control External Devices 2.1 INTRODUCTION

      10  3 Introduction to FSM Synthesis 3.1 INTRODUCTION 3.2 TUTORIALS COVERING CHAPTERS 1, 2, AND 3

      11  4 Asynchronous FSM Methods 4.1 INTRODUCTION TO ASYNCHRONOUS FSM 4.2 SUMMARY 4.3 TUTORIALS

      12  5 Clocked One Hot Method of FSM Design 5.1 INTRODUCTION 5.2 TUTORIALS ON THE CLOCKED ONE HOT FSM METHOD

      13  6 Further Event‐Driven FSM Design 6.1 INTRODUCTION 6.2 CONCLUSIONS

      14  7 Petri Net FSM Design 7.1 INTRODUCTION 7.2 TUTORIALS USING PETRI NET FSM 7.3 CONCLUSIONS

      15  Appendix A1: Boolean Algebra A1.1 BASIC GATE SYMBOLS A1.2 THE EXCLUSIVE OR AND EXCLUSIVE NOR A1.3 LAWS OF BOOLEAN ALGEBRA A1.4 EXAMPLES OF APPLYING THE LAWS OF BOOLEAN ALGEBRA A1.5 SUMMARY

      16  Appendix A2: Use of Verilog HDL and Logisim to FSM A2.1 THE SINGLE‐PULSE GENERATOR WITH MEMORY CLOCK‐DRIVEN FSM A2.2 TEST BENCH MODULE AND ITS PURPOSE A2.3 USING SYNAPTICAD SOFTWARE A2.4 MORE DIRECT METHOD A2.5 A VERY SIMPLE GUIDE TO USING THE LOGISIM SIMULATOR A2.6 USING FLIP‐FLOPS IN A CIRCUIT A2.7 EXAMPLE SINGLE‐PULSE FSM A2.8 HOW TO USE THE SIMULATOR TO SIMULATE THE SINGLE‐PULSE FSM A2.9 USING LOGISIM WITH THE TRUTH TABLE APPROACH A2.10 SUMMARY

      17  Appendix A3: Counters, Shift Registers, Input, and Output with an FSM A3.1 BASIC DOWN SYNCHRONOUS BINARY COUNTER DEVELOPMENT A3.2 EXAMPLE OF A FOUR‐BIT SYNCHRONOUS UP COUNTER WITH T TYPE FLIP‐FLOPS A3.3 PARALLEL LOADING COUNTERS – USING T FLIP‐FLOPS A3.4 USING D FLIP‐FLOPS TO BUILD PARALLEL LOADING COUNTERS A3.5 SIMPLE BINARY UP COUNTER WITH PARALLEL INPUTS A3.6 CLOCK CIRCUIT TO DRIVE THE COUNTER (AND FSM) A3.7 COUNTER DESIGN USING DON’T CARE STATES A3.8 SHIFT REGISTERS A3.9 DEALING WITH INPUT AND OUTPUT SIGNALS USING FSM A3.10 USING LOGISIM TO WORK WITH LARGER FSM SYSTEMS A3.11 SUMMARY

      18  Appendix A4: Finite State Machines Using Verilog Behavioural Mode A4.1 INTRODUCTION A4.2 THE SINGLE‐PULSE/MULTIPLE‐PULSE GENERATOR WITH MEMORY FSM A4.3 THE MEMORY TESTER FSM REVISITED A4.4 SUMMARY

      19  Appendix A5: Programming a Finite State Machine A5.1 INTRODUCTION A5.2 THE PARALLEL LOADING COUNTER A5.3 THE MULTIPLEXER A5.4

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