Frame 1.21 The Timing Waveform Diagram Solution
The solution is, of course, based on the secondary state assignments used, so your solution could well be different if you have used a different SSV pattern.
In this solution (Figure 1.23), the author has deliberately arranged for the x input to change to logic 0 inside of the clock pulse equal to 1 in state s3 just to illustrate the effect that this would have on the output P. You can see that the output pulse on P is not a full clock high period.
Figure 1.23 Timing diagram showing the effect of input x on output P.
This is a very realistic event since the outside world input x (and, indeed, any outside world input) can occur at any time.
Turn to Frame 1.22.
At this point in the course we have covered the basics of what an FSM is and how a state diagram can be developed for a particular FSM design.
The reader has also seen how the outputs of the FSM depend upon the SSVs (these are covered in Chapter 3).
The SSVs can be arbitrarily assigned, but that following a unit distance code is good practice.
The reader has looked at a number of simple designs and seen how a Mealy or Moore FSM can be realized in the way in which the output equations are formed.
We have not yet seen how the state diagram can be realized as a circuit made up of logic gates and flip‐flops, but this part of the development process is very much a mechanized activity which is covered in detail in Chapter 3.
The next section looks at a number of FSM designs in an attempt to give you some feel for the design of state diagrams for FSMs. The pace will be a little quicker as I will assume that you have understood the previous work.
You may like to take a well‐earned break at this point!
For more details, see Minns (1995).
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