referred to as the secondary state variables (SSVs) (Figure 1.16).
Figure 1.16 Block diagram showing secondary state variables in the FSM.
They are called ‘secondary state variables’ because they are (from the FSM architecture viewpoint) internal to the FSM (i.e. secondary not primary). If we consider the outside world inputs and outputs as being primary then it seems sensible to call the flip‐flop outputs SSVs (and state variables because they define the states of the state machine).
Moore and Mealy state diagram
The outputs in our FSM are seen to be dependent upon the SSVs or flip‐flops internal to the FSM. If you look back to Frame 1.5 you will see that Moore FSM outputs are dependent upon the flip‐flop outputs only. The output decoding logic in our P pulse example is:
That is it consists of an AND gate and a NAND gate. This means that a single P pulse is a Moore FSM.
How could we make our single‐pulse design into a Mealy FSM?
One way would be to make the output P depend on the FSM being in state s1 (A/B), but we could say that the output was to be the width of a single logic 0 of the clock pulse.
How would we modify our state diagram to do this?
Try doing this, and then turn to Frame 1.16 to find out if you got it right.
The modified state diagram is shown in Figure 1.17 (the r signal here has been dropped so we are back to a simple one‐pulse FSM). Also, /clk is clk inverted.
Figure 1.17 State diagram with Mealy output P.
Notice that now the output P is only equal to logic 1 when:
FSM is in state s1 where flip‐flop outputs are A = 1 and B = 0.
The clock signal is logic 0, as indicated by P = /clk.
Therefore, when the FSM enters state s1, the P output will be equal to logic 0 since /clk = 0 when the clock ‘clk’ is logic 1.
The clock will be logic 1 when the FSM enters state 1 (0 to 1 transition) the clock clk will then go to logic 0 (whilst still in state s1), and P will go to logic 1, then, when the clock clk goes back to logic 1 the FSM will move to state s2 and the flip‐flop outputs will no longer be A/B so the P output will not go high again. Therefore, the P output will only be logic 1 for a single clock clk pulse in state s1 when clk = 0 at the end of the state s1.
Figure 1.18 illustrates this more clearly.
Figure 1.18 Timing diagram showing Moore and Mealy outputs.
The waveforms show both versions of P. As you can see, the Moore version raises P for the whole duration that the FSM is in state s1, whilst the Mealy version raises P for the time that the clock is low during state s1. Note in Figure 1.18P = A/B·/Clk is not the same as P = A/B·clk.
Note the narrow pulse in the P Mealy signal during the second clk pulse. This is a glitch caused by signal delays in the A and clk signal lines. (See Chapter 4 for more on this, but for now just accept it.)
There is quite a lot going on here so you might want to re‐read this frame again to fully understand it. We will be looking at the idea of using more Mealy outputs later on in this book.
It is possible to design state diagrams without Mealy outputs, using only Moore outputs. However, sometimes it is possible to reduce the size of a state diagram (less number of states) by using Mealy outputs. Examples are shown later.
Now for something a bit different.
Try producing a state diagram for an FSM that will produce a 101 pattern in response to an s input going high. Signal s must be returned low before another 101 pattern can be produced. In this example you are trying to use each state to produce the 101 pattern.
When you have attempted this task, turn to Frame 1.17.
The solution to this problem is to use the basic arrangement of the single‐pulse state diagram and insert more states to generate the required 101 pattern (Figure 1.19).
Figure 1.19 Development of a 101 pattern generator sequence.
It will develop state by state so you can see how it is done.
Note that we must leave state s3 on a clock pulse so that P = 1 for the duration of a single clock pulse only.
The final state required is to monitor for the input s = 0 condition.
This state should return the FSM back to state s0.
1 Complete the FSM state diagram then turn to Frame 1.18.
