18.5.2 NOT gate clock zones
18.5.3 Majority voter clock zones
19 QCA adder and subtractor
19.2 The QCA half-adder and half-subtractor
19.3 The QCA full-adder and full-subtractor
19.3.1 Implementation of the full-adder and full-subtractor
20 The QCA multiplier and divider
20.1.1 Multiplication networks
20.1.2 QCA multiplication networks
20.2.1 The non-restoring binary divider
21 QCA asynchronous and synchronous counters
21.1.1 The dual-edge triggered J-K flip-flop
21.1.2 The design of dual-edge triggered J-K flip-flop
21.1.3 The asynchronous backward counter
21.2.1 QCA synchronous counters
22 The QCA decoder and encoder
22.2.1 The QCA turbo encoder design
22.2.2 The RC encoder with single-feedback
22.2.3 The RC encoder with multi-feedback
23 The QCA multiplexer and demultiplexer
23.1 The QCA 2-to-1 multiplexer
23.2 The QCA 4-to-1 multiplexer
23.3 The QCA 1-to-2 demultiplexer
23.4 The QCA 1-to-4 demultiplexer
23.5 Multiplexing/demultiplexing using QCA
23.5.1 The effect of the selector line (S0,S1) on the 2-to-1 MUX/1-to-2 DEMUX
24 The QCA RAM, ROM, and processor
24.3.3 The arithmetic logic unit
