which uses the PC added to a displacement to fetch the operand's address (EA = (PCinstruction + 1 + displacement) in the case of PDP-11).
1.2.3.4. Indexed and based addressing modes
Indexed addressing is characterized by using an Index Register (IR) that contains a reference address, called a base or offset address, making it possible to access a memory location. The content of this register, here R, is added to a displacement A specified with the instruction (Figure 1.16). The effective address EA is equal to:
[1.6]
Indexed addressing with null displacement is identical to register indirect addressing. This mode is equivalent to relative addressing if the index register is replaced by the PC (Program Counter). The index register may be implicit or designed explicitly as an operand. It can be dedicated specifically to this usage or it can be a GPR. In the former case, it is generally named X or Y (in the case of MCS6502). From the perspective of execution complexity, it adds an operation (addition) compared to the indirection. The @ symbol is generally used in assembly language to indicate this mode.
Figure 1.16. Execution of an instruction in indexed addressing with displacement (indexation “true”)
Cushman (1975) speaks of “true” and “false” indexing. Indexing is called “true” when the index address is the operand, the case in Figure 1.16 and MPUs MCS6502 and 2650 (Signetics). In the second case, the index address is in the dedicated register and the operand is the index, one example being the MC6802/MC6809 (Figure 1.17). The second field of the instruction word, called a “modifier” in Simpson and Terrell (1987) has an 8-bit format, while the index register format has 16 bits. Some manufacturers such as Motorola consider the relative address as an indexed mode, the indirection register being the PC (Program Counter, cf. § 1.2.3.3).
Figure 1.17. Execution of an instruction in indexed addressing with displacement (false indexing)
As for indirection with auto-increment or auto-decrement, auto-indexing can be suggested with the addition of an integer A to the value of the register R. The designer of M68HC12 speaks of pre-decrement and post-decrement indexed. At each execution, we will have:
[1.7]
Relative addressing is similar to an indexed addressing by the PC (Program Counter). It is for this reason that DEC (1983) called it “PC-relative addressing mode”.
Scaled indexed addressing mode makes it possible to multiply the content of the index register by a constant 1, 2, 4 or 8, for example, for 80386. This facilitates management of data structures in high-level languages as an array, a structure or record.
Base (plus) offset addressing arises from the principle above except that the index register is replaced by a base register (Figure 1.18), hence its other name: base register addressing. Intel uses the BX and BP (Base Pointer) for x86, the first addresses the data segment and the second addresses the stack. The IBM z System mainframe computer uses 16 General-Purpose Registers (GPR) in 64-bit format as a base register and the displacement is specific to the 12-bit format. At its origin, this mode made it possible to extend the address space. Today, this is no longer necessary.
Figure 1.18. Execution of an instruction in base addressing with displacement
The difference between these two modes is more semantic than applicable to calculating the effective address. The index varies starting from a given index address with the instruction, while the base address is constant (hence its name) and an offset is provided with the instruction. Moreover, Intel uses the terms “base” and “indexed” for base addressing. Moreover, if no offset is specified with the instruction, Intel (1989) names the 8086 base and indexed addressing without offset “indirect register addressing”. Often, in RISC microprocessors such as Arm®, the r0 register contains the constant 0, thus avoiding an immediate addressing using a main memory access that takes a great deal of time. If it is used as a base register, the addressing becomes absolute. The base mode is similar to segmented addressing (this will be covered in a future book by the author on memories). Another means of differentiating these two addressings is that there is no auto-increment with base addressing.
Calculation of the effective addressing depends on the storage order or endianness (cf. § V1-2.2.1) of the address' bytes. Thus, MCS6502 with a little- endian order is favored because the addition is carried out starting from the LSBs.
1.2.3.5. Combinations of addressing modes
It is possible to combine the addressing modes above. Some processors offer indirect addressing with indexing. The associated terms “pre-indexing” and “post-indexing” will qualify at what step of the address calculation the indexing will apply. Pre-indexing means that indexing is carried out on the indirection address (pre-indexed indirect addressing mode), hence the second name, “indexed indirect addressing mode”.
We will have:
Figure 1.19 shows the mechanism. One example was MCS6502, which included two registers called “index registers X and Y” even though X has already served for indirection. Its designer calls this mode (indirect,X), which is justified by the relationship [1.8]. It was also suggested by MC6809. DEC used the term “index deferred addressing mode”.
Figure 1.19. Indirect indexed addressing or pre-indexing
Post-indexed indirect addressing mode or indirect indexed addressing mode applies indexing after indirection, as illustrated in Figure 1.20. We will have:
[1.9]
Figure 1.20. Indirect indexed addressing or post-indexing
