1.12(a) shows the p-n junction circuit in the state of thermal equilibrium and the corresponding energy band diagram is shown in Figure 1.12(b) [10,11,23,24]. It is clear that the built-in-potential is Vbi across the junction formed by p- and n-blocks, while potential energy difference from p- to n-block is qVbi. On applying positive potential Vf so that the p-n junction is forward-biased, width of the barrier is reduced due to the fact that the resultant electrostatic potential across the semiconductor junction becomes Vbi − Vf as shown in Figure 1.12(c) & (d). In case of reverse biasing the p- and n-type blocks, the p-n junction barrier is reverse-biased so that the resultant electrostatic potential at the junction becomes Vbi + Vr enhancing the overall width of the depletion layer. This almost ceases the transport of charge carriers across the junction because charge carriers cannot cross the wide barrier as shown in Figure 1.12(e) & (f).
Figure 1.11 The schematic shows the electric field distribution and the width of the depletion region or barrier. The area covered under the triangle shows the built-in-potential (Vbi). The width of the barrier is in reference to the width as shown in Figure 1.9 displaying the space charge distribution.
Depletion Capacitance
Accumulation of holes and electrons at the junction of p- and n-type blocks or layers creates a capacitive effect at the barrier. This depletion layer capacitancse can be defined as
(1.27)
Figure 1.12 Schematic representations of barrier width and corresponding band energy diagrams of a p-n junction in (a) steady-state equilibrium condition and (b) related band energy diagram, (c) forward biasing showing forward current (I) and voltage Vf and (d) associated band energy diagram, (e) reverse-biased diode circuit showing reverse current (Ir) and voltage (Vr) and (f) correlated energy band diagram. It is clear that the width of depletion layer decreases in forward-biased circuit in (c) so that charge-carriers cross the barrier easily, while it increases in reverse-biased circuit in (e) which makes transportation of charge-carriers across the barrier difficult.
Figure 1.13 Schematic shows an arbitrarily profile of dopants when reversed bias as shown in (a). Schematics (b) and (c) show the change in space charge distribution and electric field profile as a function of the change in applied bias.
In case of forward-biased p-n junction, width of the depletion layer decreases as a result of high force exerted by electric field acting on charge carriers making them mobile which induces diffusion capacitance as well [10,23,24]. From the discussion held above, it is clear that p-n junction acts in form of a condenser in which p- and n-type blocks or layers are the two plates, while the barrier or depletion layer itself acts as a dielectric. The junction capacitance is inversely proportional to the thickness of the depletion layer from
1.2 Fabrication Technology of Diode
The fabrication technology of a semiconductor p-n junction diode involving different steps is displayed diagrammatically in Figure 1.14 [10,31]. This planar fabrication technology consists of thermal oxidation of Si wafer to grow SiO2 as the first step (a), second step (b) is the application of photoresist (PR) over SiO2, third step (c) is the patterning of PR with the help of optical lithography, fourth step (d) is the etching out of SiO2 and exposing selective surface of Si wafer, fifth step (e) is removal of the PR, sixth step (f) involves doping of impurity atoms selectively to produce p-n semiconductor junction, and the last step (g) is the metallization of the top layer and of the back side for electrical interconnects [10,31]. For the growth of high quality SiO2, wet or dry thermal oxidation process can be used.
Figure 1.14 Schematic shows diagrammatically the various steps involved in fabrication of p-n junction diode. The first step (a) is the thermal oxidation for the growth of SiO2 layer, second step (b) is the application of resist over the grown SiO2 layer, third step (c) is the patterning of resist, fourth step (d) involves etching out SiO2, fifth step (e) is the removal
