14.1 The controller of the original synchronverter.
Figure 14.2 Active power regulation in a conventional synchronverter after decoupling.
Figure 14.3 Properties of the active power loop of a conventional synchronverter with Xpu = 0.05, ωn = 100π rad s−1, and α = 0.5%.
Figure 14.4 VSM with virtual inertia and virtual damping.
Figure 14.5 The small‐signal model of the active‐power loop with a virtual inertia block Hv(s).
Figure 14.6 Implementations of a virtual damper.
Figure 14.7 A VSM in a microgrid connected to a stiff grid.
Figure 14.8 Normalized frequency response of a VSM with reconfigurable inertia and damping.
Figure 14.9 Effect of the virtual damping (Jv = 0.2 s).
Figure 14.10 A microgrid with two VSMs.
Figure 14.11 Two VSMs operated in parallel with Jv1 = Jv2 = 1 s.
Figure 14.12 Two VSMs operated in parallel with Jv1 = 0.5 s and Jv2 = 1 s.
Figure 14.13 Simulation results under a ground fault with Jv = 0.1, 0.3, 0.5, 1 s.
Figure 14.14 Experimental results with reconfigurable inertia and damping.
Figure 14.15 Experimental results from the original synchronverter for comparison.
Figure 14.16 Experimental results showing the effect of the virtual damping with Jv = 0.2 s.
Figure 14.17 Experimental results when two VSMs with the same inertia time constant are in parallel operation.
Figure 14.18 Experimental results when two VSMs with different inertia time constants operated in parallel.
Figure 14.19 Experimental results when the two VSMs operated as the original SV in parallel operation with τω1 = τω2 = 1 s for comparison.
Figure 15.1 Block diagrams of a conventional PLL.
Figure 15.2 Enhanced phase‐locked loop (EPLL) or sinusoidal tracking algorithm (STA).
Figure 15.3 Power delivery to a voltage source through an impedance.
Figure 15.4 Conventional droop control scheme for an inductive impedance.
Figure 15.5 Conventional droop control strategies.
Figure 15.6 Linking the droop controller in Figure 15.4(b) and the (inductive) impedance.
Figure 15.7 Droop control strategies in the form of a phase‐locked loop.
Figure 15.8 The conventional droop controller shown in Figure 15.4(a) after adding two integrators and a virtual impedance.
Figure 15.9 The synchronization capability of the droop controller shown in Figure 15.8.
Figure 15.10 Connection of the droop controlled inverter to the grid.
Figure 15.11 Regulation of the grid frequency and voltage in the droop mode.
Figure 15.12 Robustness of synchronization against DC‐bus voltage changes.
Figure 15.13 System response when the operation mode was changed.
Figure 16.1 A single‐phase inverter.
Figure 16.2 Controller to achieve a resistive output impedance.
Figure 16.3 Controller to achieve a capacitive output impedance.
Figure 16.4 Typical output impedances of L‐, R‐, and C‐inverters.
Figure 16.5 Two R‐inverters operated in parallel.
Figure 16.6 Conventional droop control scheme for R‐inverters.
Figure 16.7 Experimental results: two R‐inverters in parallel with conventional droop control.
Figure 16.8 Robust droop controller for R‐inverters.
Figure 16.9 Experimental results for the case with a linear load when inverters have different per‐unit output impedances: with the robust droop controller (left column) and with the conventional droop controller (right column).
Figure 16.10 Experimental results for the case with a linear load when inverters have the same per‐unit impedance: with the robust droop controller (left column) and with the conventional droop controller (right column).
Figure 16.11 Experimental results for the case with the same per‐unit impedance using the robust droop controller: with Ke = 10 (left column) and Ke = 1 (right column).
Figure 16.12 Experimental results with a nonlinear load: with the robust droop controller (left column) and with the conventional droop controller (right column).
Figure 16.13 Robust droop controller for C‐inverters.
Figure 16.14 Experimental results of C‐inverters (left column) and R‐inverters (right column) with a linear load RL = 9 Ω.
Figure 16.15 Experimental results of C‐inverters (left column) and R‐inverters (right column) with a nonlinear load.
Figure 16.16 Robust droop controller for L‐inverters.
Figure 16.17 Experimental results of L‐inverters with a linear load: with the robust droop controller (left column) and the conventional droop controller (right column).
Figure 16.18 Experimental results of L‐inverters with a nonlinear load: with the robust droop controller (left column) and with the conventional droop controller (right column).
Figure 17.1 The model of a single‐phase inverter.
Figure 17.2 The closed‐loop system consisting of the power flow model of an inverter and a droop controller.
Figure 17.3 Interpretation of transformation matrices TL and TC.
Figure 17.4 Interpretation of the universal transformation matrix T.
Figure
