17.6 Real‐time simulation results of three inverters with different types of output impedance operated in parallel.
Figure 17.7 Experimental set‐up consisting of an L‐inverter, an R‐inverter, and a C‐inverter.
Figure 17.8 Experimental results with the universal droop controller.
Figure 18.1 The self‐synchronized universal droop controller.
Figure 18.2 Experimental results of self‐synchronization with the R‐inverter.
Figure 18.3 Experimental results when connecting the R‐inverter to the grid.
Figure 18.4 Experimental results with the R‐inverter: performance during the whole experimental process.
Figure 18.5 Experimental results with the R‐inverter: regulation of system frequency and voltage in the droop mode.
Figure 18.6 Experimental results with the R‐inverter: change in the DC‐bus voltage VDC.
Figure 18.7 Experimental results of self‐synchronization with the L‐inverter.
Figure 18.8 Experimental results with the L‐inverter: connection to the grid.
Figure 18.9 Experimental results with the L‐inverter: performance during the whole experimental process.
Figure 18.10 Experimental results with the L‐inverter: regulation of system frequency and voltage in the droop mode.
Figure 18.11 Experimental results with the L‐inverter: change in the DC‐bus voltage VDC.
Figure 18.12 Experimental results of self‐synchronization with the L‐inverter with the robust droop controller.
Figure 18.13 Experimental results from the L‐inverter with the robust droop controller: connection to the grid.
Figure 18.14 Experimental results from the L‐inverter with the robust droop controller: performance during the whole experimental process.
Figure 18.15 Experimental results from the L‐inverter with the robust droop controller: regulation of system frequency and voltage in the droop mode.
Figure 18.16 Experimental results with the L‐inverter under robust droop control: change in the DC‐bus voltage VDC.
Figure 18.17 A microgrid including three inverters connected to a weak grid.
Figure 18.18 Real‐time simulation results from the microgrid.
Figure 19.1 A general three‐port converter with an AC port, a DC port, and a storage port.
Figure 19.2 DC‐bus voltage controller to generate the real power reference.
Figure 19.3 The universal droop controller when the positive direction of the current is taken as flowing into the converter.
Figure 19.4 Finite state machine of the droop‐controlled rectifier.
Figure 19.5 Illustration of the operation of the droop‐controlled rectifier.
Figure 19.6 The θ‐converter.
Figure 19.7 Control structure for the droop‐controlled rectifier.
Figure 19.8 Experimental results in the GS mode.
Figure 19.9 Experimental results in the NS‐H mode.
Figure 19.10 Experimental results in the NS‐L mode.
Figure 19.11 Transient response when the system starts up.
Figure 19.12 Transient response when a load is connected to the system.
Figure 19.13 Experimental results showing the capacity potential of the rectifier: real power P, grid voltage Vg, DC‐bus voltage vDC, and Δϕ.
Figure 19.14 Controller for the conversion leg.
Figure 19.15 Comparative experimental results with a conventional controller.
Figure 20.1 A grid‐connected single‐phase inverter with an LCL filter.
Figure 20.2 The equivalent circuit diagram of the controller.
Figure 20.3 The overall control system.
Figure 20.4 Controller states.
Figure 20.5 Implementation diagram of the current‐limiting universal droop controller.
Figure 20.6 Operation with a normal grid.
Figure 20.7 Transient response of the controller states with a normal grid.
Figure 20.8 Operation under a grid voltage sag 110 V → 90 V → 110 V for 9 s.
Figure 20.9 Controller states under the grid voltage sag 110 V → 90 V → 110 V for 9 s.
Figure 20.10 Operation under a grid voltage sag 110 V → 55 V → 110 V for 9 s.
Figure 20.11 Controller states under the grid voltage sag 110 V → 55 V → 110 V for 9 s.
Figure 21.1 Two systems with disturbances interconnected through ΣI.
Figure 21.2 Two systems with disturbances and external ports interconnected through ΣI.
Figure 21.3 Three‐phase grid‐connected converter with a local load.
Figure 21.4 The controller for a cybersync machine with e to be supplied as u.
Figure 21.5 The mathematical structure of the system constructed to facilitate the passivity analysis, where the plant pair ΣP consists of the original plant and its ghost in grey and the input to the ghost plant is the ghost of the input to the plant.
Figure 21.6 Blocks Σω and Σφ implemented with the IC.
Figure 21.7 A cybersync machine equipped with regulation and self‐synchronization.
Figure 21.8 Simulation results from a cybersync machine, where the detailed transients indicated by the arrows last for five cycles with the magnitude reduced by 50%.
Figure 21.9 Experimental results from a cybersync
