Reversible and DNA Computing. Hafiz M. H. Babu

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Register.Table 16.3 Truth Table of the Fault‐Tolerant F2PG Gate.Table 16.4 Truth Table of the NFTFAG.

      15 Chapter 17Table 17.1 Truth Table of F2G and FRG GateTable 17.2 Truth Table of

‐to‐ Decoder with One Constant InputTable 17.3 Truth Table of Figure 17.12 (a)Table 17.4 Truth Table of Figure 17.12 (b)

      16 Chapter 19Table 19.1 Frequency Matrix Based on Multi‐Output Function, F.Table 19.2 Calculation of Number of Product of Functions.Table 19.3 Truth Table of Reversible Fault Tolerant MSH Gate.Table 19.4 Truth Table of Reversible Fault‐Tolerant MSB Gate

      17 Chapter 20Table 20.1 Truth Table of

Reversible Fault‐Tolerant UPPG GateTable 20.2 Truth Table of Group‐1 PP CellTable 20.3 Different Functions of Fault‐Tolerant ALU

      18 Chapter 21Table 21.1 Truth Table of Reversible Logic Gate R1Table 21.2 Truth Table of Reversible Logic Gate R2Table 21.3 Truth Table of Reversible Logic Gate R3

      19 Chapter 22Table 22.1 Truth Table of UFT Gate.

      20 Chapter 27Table 27.1 Sequence list

      List of Illustrations

      1 Chapter 1Figure 1.1 A

reversible gate.Figure 1.2 Popular reversible gates.Figure 1.3 Reversible Feynman gate.Figure 1.4 Quantum realization of reversible Fredkin (FRG) gate.Figure 1.5 The quantum representation of reversible HNG gate.Figure 1.6 Block diagram of the reversible FRG gate.Figure 1.7 Quantum representation of a reversible FRG gate.Figure 1.8 Toffoli gates as self‐reversible.Figure 1.9 Quantum cost calculation of Feynman gate.Figure 1.10 Quantum circuit of Toffoli gate.Figure 1.11 Quantum circuit of Fredkin gate.Figure 1.12 Quantum circuit of a Peres gate.

      2 Chapter 2Figure 2.1 Multi‐operand n‐digit decimal adder.Figure 2.2 The architecture of reversible multi‐operand n‐digit decimal adde...Figure 2.3 The architecture of reversible single‐digit block of m‐operand n‐...Figure 2.4 4

4 reversible FAG gate.Figure 2.5 Reversibility of 4

4 reversible FAG gate.Figure 2.6 Reversible FAG gate as full adder.Figure 2.7 The n‐bit carry skip adder circuit.Figure 2.8 Single block carry skip adder circuit.Figure 2.9 Reversible CSA for single digit.Figure 2.10 Reversible carry skip circuit.Figure 2.11 Reversible partial full adder.Figure 2.12 n‐bit CLA adder circuit.Figure 2.13 A 1‐digit BCD adder's overflow detection logic.Figure 2.14 A 1‐bit BCD adder correction logic circuit.Figure 2.15 A 1‐digit BCD adder.Figure 2.16 A carry skip 1‐digit BCD adder.Figure 2.17 Nine's complement circuit.Figure 2.18 Modified nine's complement circuit.Figure 2.19 Modified conventional BCD subtractor.Figure 2.20 CLA BCD subtractor.Figure 2.21 Carry skip BCD subtractor.Figure 2.22 Reversible nine's complement.Figure 2.23 Reversible BCD subtractor.Figure 2.24 Reversible CLA BCD subtractor.Figure 2.25 Reversible logic implementation of the carry skip BCD adder.

      3 Chapter 3Figure 3.1 Process of 4

4 multiplications.Figure 3.2 Block diagram of a reversible HNG gate.Figure 3.3 The quantum representation of a reversible HNG gate.Figure 3.4 Symbols of the controlled‐T and controlled‐

gate.Figure 3.5 5

5 BSJ gate and its corresponding input–output mapping.Figure 3.6 Quantum realization of 5

5 BSJ gate.Figure 3.7 3

3 MPG and its corresponding input–output mapping.Figure 3.8 Quantum realization of 3

3 MPG.Figure 3.9 Quantum analysis of 3

3 MPG.Figure 3.10 A compact quantum realization of 3

3 MPG.Figure 3.11 Block diagram of R cell.Figure 3.12 Construction of R cell.Figure 3.13 3

3 MTG and its corresponding input–output mapping.Figure 3.14 Quantum realization of 4

4 MTG.Figure 3.15 3

3 MFRG and its corresponding input–output mapping.Figure 3.16 Quantum realization of 4

4 MFRG.Figure 3.17 A Compact quantum realization of 4

4 MFRG.Figure 3.18 16

16 PPG array.Figure 3.19 Gate level diagram of a 4

4 PPG for reversible Booth's multipl...Figure 3.20 Block diagram of an

PPG for reversible Booth's multiplier.Figure 3.21 Gate level diagram of a 4

4 MOA for reversible Booth's multipl...Figure 3.22 Diagram of an n

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