Nanogap cavity is formed by the process of etching gate oxide in the channel from both the sides of source and drain
Detecting biomolecules such as DNA, enzymes, cells etc using dielectric modulation technique. The channel length is 100 nm.
[8]
Graded channel dual material gate junctionless (GC-DMGJL) MOSFET
The GC-DMGJL MOSFET gives high drain current and transconductance and also reduces short-channel effects. The channel length is 30 nm.
[9]
Black phosphorus is integrated with the junctionless recessed MOSFET
Structure drain current increases up to 0.3 mA. The off current reduces, improvement in subthreshold slope. The channel length is 44 nm.
[10]
Fully depleted tri material double-gate MOSFET is used
Improvement in the RF performance, linearity and analog performance compared to the DM-DG MOSFET and single material DG MOSFET. The channel length is 35 nm.
[11]
Pocket region is constructed near the source and drain region and is heavily doped
Good immunity from short-channel effects and can meet the specifications of OFF-state current and ON-state current. The channel length is 100 nm.
[12]
A transparent gate recessed channel is used
Enhancement of cut-off frequency by 42% and oscillator frequency is increased by 32%. The channel length is 30nm.
[13]
MOSFET with asymmetrical gate to improve the functioning of the device
Decrease in subthreshold slope (68 mV/dec) and drain induced barrier lowering (65 mV/V). The channel length is 20 nm.
[14]
6-T SRAM cell using silicon on insulator
The area of the junctionless transistor-based 6-T SRAM cell using silicon on inductor is 6.9 μm-cube and that of the conventional structure is 11.3 μm -cube.
[15]
Short-channel dual metal gate with recessed source and drain SOI MOSFET
This device provides high on current, low DIBL value. The channel length is 30 nm -300nm.
[16]
Dual Material Surrounding Gate MOSFET to suppress short-channel effects
DMSG MOSFET (SCEs) more efficient as compared to a conventional SMSG MOSFET
[17]
Misalignment effect introduced by the asymmetrical source and drain
The region which is non-overlapped produces extra series resistance and weak control over the channel, while the additional overlapped region produces extra overlap capacitance and supply to ground leakage current through gate
[18]
Optimized the design of the gate all around MOSFET and compared it with the double gate MOSFET
GAA structure reduced the DIBL value to 81.44 mV/V when compared to the double-gate MOSFET. The ON-state current is increased and OFF-state current is reduced.
[19]
The deviation in the oxide thickness between the two gates is considered small. A surface potential solution is used for symmetric double-gate MOSFET for initial trial approximation for approaching surface potential solution for asymmetric double-gate MOSFET.
Different parameters of MOSFET like drain current, 5channel current, transconductance, gate capacitances and the effect of oxide thickness on these parameters are determined.
[20]
Performance analysis of junctionless double-gate MOSFET based 6T SRAM with gate stack configuration
The use of high k dielectric material in the junctionless DG-MOSFET shows improvement in static noise margin. Scaling down of gate length degrades the stability.
[21]
Simulation of junctionless double-gate MOSFET with symmetrical side gates. With the presence of side gates the channel present under the front gate, is electrically insulated from the drain voltage resulting to electron shielding.
The DIBL and SS values improved using the side gates. The drain voltage effect on the channel is reduced so it becomes easy for the gate to have more control over the channel.
[22]
A structure of double-gate MOSFET with symmetrical insulator packets for improving the SCEs. In this, insulator packets were inserted between the channel junction and source/ drain ends
Hot electron reliability improves. There is an improvement in the DIBL value and ON/OFF-state current ratio.
Figure 1.4 shows the performance of MOSFET when different gate contacts are used like aluminium, polysilicon and copper. MOSFET shows better performance when polysilicon is used as a gate contact. Metal gates like Aluminium and copper operate at voltages 3V to 5V. The lowering of operating voltages leads to the use of polysilicon gate contact. From the graph we can observe at lower operating voltages polysilicon gate contact gives better performance because the OFF-state current is low.
Figure 1.3 Id Versus Vgs plot with different oxide region material.
The proposed JL-DG MOSFET has ratio of 1013 which is higher than other existing structures. The calculation of SCE parameters like SS and DIBL is also a deciding factor for device performance. The proposed device show SS value of 59 mV/ decade and DIBL of 13.4 mV/V. Both SS and DIBL values are less than other existing transistors. Therefore, heavily doped AJ-DG MOSFET has superior ON/OFF performances.
Figure 1.4 Id versus Vgs Plot of different gate contact material.
Nanogap cavity is formed by the process of etching gate oxide in the channel from both the sides of source and drain
