MOSFETs were designed with a nanogap cavity region as bio-sensor that can sense the bio-molecule present in the nanogap cavity [23, 24]. These bio-sensors work on the principle of dielectric modulation with the variation in bio-species present in the air (nanogap cavity) that further varies the electrical parameters of the device.
Figure 1.5 shows the 2-D view of JL-DG MOSFET with a cavity region. Here the cavity plays an important role to sense the bio-species present in air. The presence of bio-species and their concentration affect the dielectric constant of the cavity region that further affects the electrical parameters of transistor. The cavity region with different length (Lcavity) and height (Hcavity) shows varied device sensitivity towards the presences of biomolecules. This effect has been studied through varying dielectric constant with different materials such as air, SiO2, HfO2 and S3N4.
Figure 1.5 shows AJ-DG MOSFET with the nanogap cavity region. A thin SiO2 layer used for binding the molecules entering the cavity region by restricting the movements of bio-molecules. For the presented device the cavity region height (Hcavity) is 2.7 nm and SiO2 layer thickness is 0.3 nm. Another way to analyze device sensitivity is by introducing different types of charged particles in the cavity region.
In Figure 1.6 a sharp change is observed in the threshold voltages with the different dielectric constant of the material added in the cavity region. The longer cavity region length shows more variations in threshold voltage that results in the shifting of channel inversion threshold level. Therefore with a higher value of dielectric constant, the threshold voltage lowers. This shows that the device is highly sensitive towards the change in dielectric material constant depending on biomolecule presence resulting in electrical parameter variations.
A significant variation in threshold voltage is observed with a change in oxide thickness. The changing oxide thickness results in a change in the cavity region thickness that also affects the electrical parameter variations.
1.6 Conclusion
The AJ-DG MOSFET is a suitable choice for low-power applications such as bulk memories that are integral parts of many IoT-enabled systems. The performance of AJ-DG MOSFET can also be varied by adjusting the position of the top and bottom gate overlapping regions. High ON/OFF current ratio and low leakage current are the key features of the AJ-DG MOSFET with low static power consumption and enhanced speed of circuit operation. Another application of JL-DG MOSFET is as biosensor by introducing cavity region between gate and channel. These cavity regions are sensitive to the bio species present in the environment. The variation in biomolecule changes the dielectric constant of the medium that results in the variation in electrical parameters of a device that can be easily measured to detect the presence of bio-species.
Figure 1.6 Id Versus Vgs of AJ-DG MOSFET with varying dielectric constant (Lcavity = 7nm).
References
1. S L Tripathi, Ramanuj Mishra, R A Mishra, “Characteristic comparison of connected DG FINFET, TG FINFET and Independent Gate FINFET on 32 nm technology” IEEE ICPCES, pp. 1-7, December, 2012.
2. Ammina, V.P., Vankudothu, S.P., Shaik, R.R. et al. An Optimized Ge Pocket SOI JLT with Efforts to Improve the Self-Heating Effect: Doping & Materials Perspective. Silicon, 2019. https://doi.org/10.1007/s12633-019-00319-x
3. F. Djeffal, H.Ferhat, T.Bentrcia. Improved analog and RF performances of gate-all-around junctionless MOSFET with drain and source extensions, Superlattices and Microstructures, 90, 132-140, 2016.
4. Nirmal Ch. Roy, Abhinav Gupta, Sanjeev Rai. Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits, Microelectronics Journal, 46 (10), 916-922, 2015.
5. E. Chebaki, F.Djeffal, H.Ferhati, T.Bentrcia. Improved analog/RF performance of double gate junctionless MOSFET using both gate material engineering and drain/source extensions, Superlattices and Microstructures, 92, 80-91, 2016.
6. Ali A. Orouji, M. Jagdeesh. Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects, Superlattices and Microstructures, 39(5), 395-405, 2006.
7. Ajay, Rakhi Narang, Manoj Saxena, Mridula Gupta. Investigation of dielectric modulated (DM) double gate (DG) junctionless MOSFETs for application as a biosensors, Superlattices and Microstructures, 85, 557-572, 2015.
8. Varsha Pathak, Gaurav Saini. A Graded Channel Dual-Material Gate Junctionless MOSFET for Analog Applications, Procedia Computer Science, Vol. 125, 825-831, 2018.
9. Ajay Kumar, M.M.Tripathi, Rishu Chaujar. Analysis of sub-20 nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications, Superlattices and Microstructures, 116, April 171-180, 2018.
10. Angsuman Sarkar, Aloke Kumar Das, Swapnadip De, Chandan Kumar Sarkar. Effect of gate engineering in double-gate MOSFETs for analog/RF applications, Microelectronics Journal, 43(11), 873-882, 2012.
11. Yon-Sup Pang, John R Brews. Design of 0.1-lm pocket n-MOSFETs for low-voltage applications, Solid-State Electronics, 46(12), 2315-2322, 2002.
12. Ajay Kumar, Neha Gupta, Rishu Chaujar. TCAD RF performance investigation of Transparent Gate Recessed Channel MOSFET, Microelectronics Journal, 49, 36-42, 2016.
13. Ying Wang, Yan Tang, Ling-ling Sun, Fei Cao. High performance of junctionless MOSFET with asymmetric gate, Superlattices and Microstructures, 97, 8-14, 2016.
14. Vimal Kumar Mishra, R. K. Chauhan. Efficient Layout Design of Junctionless Transistor Based 6-T SRAM Cell Using SOI Technology, ECS Journal of Solid State Science and Technology, 7(9)2018.
15. G.K. Saramekala Abirmoya Santra, Sarvesh Dubey, Satyabrata Jit, Pramod Kumar Tiwari. An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET, Superlattices and Microstructures, 60, 580-595, 2013.
16. Arobinda Pal, Angsuman Sarkar, Analytical study of Dual Material Surrounding Gate MOSFET to suppress short-channel effects (SCEs), Engineering Science and Technology, 17 (4), December 2014, pp. 205-212, 2014.
17. Chunshan, P.C.H. Chan. Investigation of the Source/Drain Asymmetric Effects Due to Gate Misalignment in Planar Double-Gate MOSFETs, IEEE Transactions on Electron Devices, 52(1), 85-90, 2005.
18. Jae Young Song, Woo Young Choi, Ju Hee Park, Jong Duk Lee, Byung-Gook Park. Design Optimization of Gate-All-Around (GAA) MOSFETs, IEEE Transaction on Nanotechnology, 5(3), 186-191, 2006.
19. Sheng Chang, Gaofeng Wang, Qijun Huang, Hao Wang. Analytic Model for Undoped Symmetric Double-Gate MOSFETs With Small Gate-Oxide-Thickness Asymmetry, IEEE Transactions
