Design and Development of Efficient Energy Systems. Группа авторов

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Electron Devices, 56(10), 2297-230, 2009.

      20. Shubham Tayal, Ashutosh Nandi. Performance analysis of junctionless DG-MOSFET-based 6T-SRAM with gate-stack configuration, Micro & Nano Letters, IET Journal, 13(6), 838-84, 2018.

      21. Bavir, M., Abbasi, A. & Orouji, A.A. A Simulation Study of Junctionless Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with Symmetrical Side Gates. Silicon (2019). https://doi.org/10.1007/s12633-019-00258-7

      22. Zeinab Ramezani, Ali A. Orouji. A Novel Double Gate MOSFET by Symmetrical Insulator Packets with Improved Short Channel Effects, International Journal of Electronics, 105(3), 361-374, 2018.

      23. Tripathi S. L., Patel R., Agrawal V. K. Low Leakage Pocket Junction-less DGTFET with Bio-Sensing Cavity Region. Turkish Journal of Electrical Engineering and Computer Sciences 27(4), 2466-2474, 2019.

      24. Mendiratta N., Tripathi S. L., Padmanaban S. and Hossain E. Design and Analysis of Heavily Doped n+ Pocket Asymmetrical Junction-Less Double Gate MOSFET for Biomedical Applications. Appl. Sci. 10, 2499, 2020.

      *Corresponding author: [email protected]

      2

      VLSI Implementation of Vedic Multiplier

       Abhishek Kumar

       School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, India

       Abstract

      Vedic arithmetic is an old Indian science, discovered from ancient Indian sculptures (Vedas). High-speed more multiple is the primary block in processor architecture. Vedic mathematics developed from a special method of calculations of 16 sutras. This chapter presents VLSI architecture implementation of an 8-bit multiplier with compressors, which shows significant improvement over conventional add shift multiplier. Vedic mathematics developed from 16 principles known as sutras. The technique of Vedic more multiple is Urdhva-Triyakbhyam (Vertically and Crosswise) sutra. This sutra was customarily used in the ancient history of Indian culture to multiply two decimal numbers with minimum time. The hardware architecture of Vedic multiplier is similar to array multiplier. In the performance of digital signal processors which frequently perform multiplication, much depends on the calculation speed of the multiplier block. The existing method of multiplication shift-add, booth multiplication requires hardware resources, which leads to high power consumption. The present method of Vedic multiplication based on the compressor block is focused on the reduction of interconnect wire. The multiplier is implemented using Verilog HDL with cadence NC SIM and the constrain areas, power and delay optimize using underlying block.

      Keywords: Vedic multiplier, urdhva-tiryakbhyam, adder, compressor, Hdl, power

      High-speed power and low-power multiplication are the fundamental blocks for high-speed processor architecture. It is hard to realize both high-speed and low-power architecture (VLSI tradeoff). There is various multiplier architecture available in the literature. Basically, the multiplier is complete by repeated addition; a full adder is a basic unit of the multiplier, cell area increases proportionally with the number of input increases. Switching power increases with interconnection among the cells. The present work of the Vedic multiplier is focused on reducing the cell count by utilizing a compressor block into the design. The compressor is a combination of multiple adder block. It accepts multiple inputs to perform addition and map the result into a lower number of the output signal.

Sutras Properties
Anurupye Shunyamanyat One is in proportion, other is zero
ChalanaKalanabyham Closeness and distinction
EkadhikinaPurven By one more than the past one
kanyunenaPurvena By one is greater than previous one
Gunakasamuchyah Elements of the whole are equivalent to the quantity of components
Gunitasamuchyah The product of sum (POS) is equivalent to sum of product (SOP)
NikhilamNavatashcaramamDashatah All from 9 and previous from 10
ParaavartyaYojayet Interchange and modify
Puranapuranabyham Completion of the non-completion
Sankalana Addition and subtraction
ShesanyankenaCharamena Remainders
ShunyamSaamyasamuccaye Sum is zero
Sopaantyadvayamantyam Twice and ultimate
Urdhva-tiryakbhyam Vertical - crosswise
Vyashtisamanstih Part – entire
Yaavadunam Extent of deficiency

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