target="_blank" rel="nofollow" href="#ulink_c03dcfc6-b8bf-5f05-8864-6d07c9d1d617">Figure 2.14 Net power usage of 8X8 VM.
Figure 2.15 Net power usage of 16X16 VM.
2.4.3 8-Bit Multiplier
Table 2.3 presents the cell area requirement of the 8x8 Vedic Multiplier. Cell area report models the number of the basic cell requires to the design. To implement this project 139 cells are required, and the area which is obtained by cells is 1517, and the net area is “zero”. The total area which is accomplished is 1517, and there is no Wire Load for this Vedic Multiplier.
Table 2.3 Cell area of 8x8 vedic multiplier.
| Instance | Cells | Cell area | Net area | Total area | Wire load |
|---|---|---|---|---|---|
| Vedic Multiplier | 139 | 1517 | 0 | 1517 | <none> (D) |
Table 2.4 Power constraints of 8x8 vedic multiplier.
| Instance | Cells | Leakage power(nW) | Dynamic power(nW) | Total power(nW) |
|---|---|---|---|---|
| vedicmultiplier | 139 | 13442.07 | 86424.01 | 99866.08 |
Table 2.5 Time constraint of 8x8 vedic multiplier.
| Pins | Type | Fan out | Load (fF) | Slew (ps) | Delay (ps) | Arrival (ps) |
|---|---|---|---|---|---|---|
| p[14] | out port | 0 | 2637 R |
An instance of an 8-bit VM named Vedic multiplier requires 139 cells in this project; there is an unwanted sub-threshold current which is leakage of power in 13422.07nW (Nano Watt). Dynamic power, a part of power that consumed while the inputs are active, obtained value is 86424.01 nW and the total power which is obtained for this 8x8 Vedic Multiplier is 99866.08 nW shown in Table 2.4.
Here pin p[14] defines that it is the last output pin of 8x8 Vedic Multiplier and type defines whether it is input port or output port. The longest path arrival time (AT) of signal is calculated as the latency for a signal to arrive at point of consideration, for this project is 2637 ps shown in Table 2.5.
2.4.4 16-Bit Multiplier
The 16x16 Vedic Multiplier requires 666 cells to implement this project, and the area which is obtained by cells is 5967, and the net area is “zero” as shown in Table 2.6. The total area in which it is accomplished is 5967, and there is no wire load for this Vedic Multiplier.
16-bit multiplier needs 666 cells to implement. Here unwanted sub-threshold current which is leakage of power in 60576.57 nW. The dynamic power of 16-bit multiplier to complete product are 444556.31 nW and the total power obtained to 505132.87 nW as shown in Table 2.7.
Table 2.6 Cell area of 16x16 vedic multiplier.
| Instance | Cells | Cell area | Net area | Total area | Wire load |
|---|---|---|---|---|---|
| 16-bit VM | 666 | 5967 | 0 | 5967 | <none> (D) |
Table 2.7 Power constraints of 16x16 vedic multiplier.
| Instance | Cells | Leakage power (nW) | Dynamic power (nW) | Total power (nW) |
|---|---|---|---|---|
| 16-bit VM | 666 | 60576.57 | 444556.31 | 505132.87 |
Table 2.8 Time constraint of 16x16 vedic multiplier.
| Pin | Type | Fanout | Load (fF) | Slew (ps) |
Delay (ps)
|
|---|
