Table 2.9 Comparison of multiplier architecture.
| 8-bit Multiplier | Leakage power (μW) | Dynamic power (micro μW) | Total power (μW) | Delay (ns) | Cell count | Cell area |
|---|---|---|---|---|---|---|
| Vedic Multiplier | 13.44 | 86.42 | 99.86 | 2.637 | 139 | 1517 |
| Booth Multiplier [21] | 5.69 | 324.53 | 330.22 | 3.75 | 214 | 5115 |
| Wallace Tree Multiplier [21] | 5.6263 | 655.55 | 661.17 | 3.02 | 248 | 1470 |
| Dadda Multiplier [21] | 5.62 | 655.807 | 2661.47 | 2.56 | 266 | 1330 |
Here pin p[30] defines that it is the last output pin of 16x16 Vedic Multiplier and type defines whether it is input port or output port. The longest path arrival time form input to pin p[30] is 5476 ps shown in Table 2.8.
The present work of 8-bit Vedic multiplier is compared with the existing different architecture of multiplier, shown in Table 2.9 in terms of power, delay and cell area. It is observed that the Dadda multiplier needs a large number of nets that require a lower area than the Wallace tree multiplier. Booth requires a lower number of cells but the total area increases to approximately three- to four-fold compare to the Wallace tree and Dadda multiplier [17–19]. Since the booth multiplication algorithm requires multiple time shifting-adding greater number of wire resources.
Vedic multiplier replaces the underlying cell by compressors logic, made up of adder block. Utilization of compressor greatly reduces the wiring resource save area. The leakage power of the Vedic multiplier is larger than other compare multipliers but shows very low dynamic power consumption. Dadda multiplier requires maximum power to reduce the delay 2.56ns. A Vedic multiplier attains significant reduction in dynamic power requirement and delay of multiplication architecture. Cell count of VM is 139 which is much smaller than other multipliers.
2.4.5 Applications of Multiplier
The present work Vedic multiplier finds application to implement the architecture of the following [21–25]
1 1) High-speed signal processing
2 2) DSP based application
3 3) DWT and DCT transformation
4 4) FIT and IIR filter
5 5) Multirate signal processing
6 6) Up-Down converters
7 7) Multiply - Accumulate unit
2.5 Conclusion
An efficient productive strategy for multiplication based on Urdhva Tiryakbhyam Sutra (Algorithm) in view of Vedic mathematics is implemented in this paper with Verilog HDL. Here a fast 8-bit multiplier is implemented that incorporates architecture of compressor. Compressor is a derived structure of full adder and half adder, map multiple input to lesser number of output signals. Hierarchical multiplier structure and shows the computational speed by offered by Vedic methods. Essential inspiration of this work is to decrease the delay in complex multiplication achieve 2.637 ns. We can deduce that the compressor-based architecture of Vedic math’s multiplier is more favorable than conventional multipliers and preferred in complex algorithm implementation. Hence, we have concluded that Instance Power usage of 8x8 Vedic Multiplier is 40.48% and 16x16 Vedic Multiplier is 62.22%. The Net Power usage of 8x8 Vedic Multiplier is 82.24%, and the 16x16 Vedic Multiplier is 86.85%.
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